Developed the key Intellectual Property for the first product, developed a thorough value proposition through in-depth market research, wrote a grant to the NSF Seed Fund, developed a full three statement model to project financial viability of the business, and continuous networking for customer relationship and customer product validation.
Mentored and managed six team members. Three were promoted to leadership roles and are now managing small teams while owning and developing major subsystems of the product. Designed, and implemented a system for routing user requests in a large scale Content Distribution Network (CDN), a major feature required for final product functionality. Deployed the staging and production clusters with a cross-functional team finalizing the product allowing the rest of the engineering org to push updates to production through CI/CD processes.
Organized and mediated review of five major system architecture specifications as head of the Architecture Review Board. These systems formed the fundamental backbone of the final product. Analyzed steady state behavior of the content delivery scheduling system for optimization and led a significant effort that increased its scalability by two orders of magnitude. Designed and implemented the event processing system including real-time evaluation of 20 different KPIs and management of dataflow for analytics.
Developed the emoji picker in 2018 for chat.google.com including front and back end design. Designed and implemented a complete development environment and circuit library for self-timed circuits in 2016 with automatic test generation and mixed-signal simulation.
Invented a variety of self-timed multipliers, exploiting irregular data patterns for efficient solutions.
Design of tests and test coverage for the power controller of the Haswell architecture in 2012 and low level cache of the Ivytown architecture in 2011. Design and implementation of a static analysis tool to automatically generate tests from coverage reports.
Development of scripts and Java plugins to extend support for two computer forensics tools: RouterMarshal and P2PMarshal.
Implemented a variety of displays for scientific experiments in human perception that have since been published. Developed other tools including a program to help assign teaching assistants, a tool for analysis of bacterial cultures, and the website for the lab.
Corporate Finance Academy, Kelley School of Business Merit Fellowship Award
Analyzed statistical behavior of program workload for optimizable features, invented a collection of arithmetic operators using those program workload features that doubled throughput per transistor and halved energy per operation on average compared to industry standard approaches.
Developed an automated formal synthesis engine for Quasi-Delay Insensitive circuits including a simulator, state space elaborator, and state conflict checker for Handshaking Expansions along with partial implementations for unique state encoding and guard strengthening.
Collaborated on the tapeout of the Braindrop chip, and was responsible for the design, verification, and layout of the asynchronous memory.
A rendering engine for large randomly generated planets with smooth level-of-detail transition from space to ground.
A full container library implemented as an educational exercise, implementing generic slices using any container of iterators.
A recipe website that calculates the ingredients that are more likely to be in a recipe with the ingredients already selected.
Four small neuron toys that can be connected together to form a simple neural network. Upon firing, a set of LEDs along the axon and dendrites light up in sequence to show a depolarization travel from one neuron to the next.
Managed the interactions between the flight computer and the sensors, keeping track of data formats, data transfer speeds, and sensor health.
A library for fast many-variable boolean operations. This encodes four-valued variable using two bits (00 is error, 01 is false, 10 is true, and 11 is unknown), packing 16 variables into a single integer so they can be operated on in parallel.
A synthesis engine for Quasi-Delay Insensitive circuits. Circuits are described as an abstract behavioral model in Communicating Hardware Processes (CHP) and formal transformations are applied to synthesize a digits circuit.
A text summary tool that extracts a vector of nouns or topic from a sentence then calculates the semantic distance between the topics of two sentences. A four-sentence window is slid over the text producing a graph of topic distance in which local minima represent paragraph boundaries. Summary sentences that best cover the topic are selected from each paragraph and concatenated allowing for the process to be repeated.