Signal Processing Architecture TrendsNed Bingham
Since the 1960s, three distinct architectures have been used to accelerate computational tasks for DSP systems: Microprocessors, Field Programmable Gate Arrays (FPGA), and Coarse Grained Reconfigurable Arrays (CGRA), all with variations optimizing the problem domain with specialization , parallelism , and configurability .
Early DSP history was myopically focused on specialization in Microprocessor architectures primarily due to limited area on die . The first single-chip DSP, the TMC 0280, was developed in 1978 with a dedicated multiply accumulate (MAC) unit , and dedicated complex operators are a mainstay of DSP architectures to this day. The TMS 32010 adopted the Harvard Architecture in 1982 to satisfy intensive IO bandwidth requirements , and numerous variations appeared shortly thereafter . The DSP 32 added floating point arithmetic to deal with data scaling issues in 1984 , and the DSP 56001 found a better solution in 1987 with saturating fixed-point arithmetic on a wide datapath . The DSP 32 also added register indirect addressing modes to compress memory addresses in the instruction words, and the DSP 56001 implemented circular buffers in memory to optimize delay computations.
With shrinking process technology nodes yielding more transistors on die, DSP architectures shifted focus toward parallelism . The TMS320C20 had a pipelined datapath to target data parallelism in 1993 . In 1996, the TMS320C8x added multiple cores to optimize task parallelism . Then in 1997, the DSP16xxx introduced a two lane pipelined Very Long Instruction Word (VLIW) architecture .
In the 2000s, the DSP market saw a fundamental shift. First, Intel introduced DSP extensions for their general purpose processors targeting non-embedded applications in 1999 . Second, Xilinx introduced FPGAs to the DSP market with the development of the Xilinx Virtex-II targeting embedded high-performance applications in 2001 . While difficult to program, FPGAs are much more flexible, have orders of magnitude better performance and energy consumption, and may be reconfigured in the field. As a result, specialized microprocessor DSP architectures were relegated to embedded low-performance problem domains. Since then, FPGA innovations have focused on application specific operator integration and network optimization , ease of use , embedded and non-embedded system integration , and run-time and partial reconfigurability .
While the dominance of FPGAs has demonstrated that array architectures are the right solution for the problem domain, CGRAs show the potential for significant improvements across the board . Historically, bit-parallel CGRAs have extremely limited capacity due to routing resource requirements. Digit-serial CGRAs solve the capacity issues by reducing the width of the datapath. However, they also sacrifice configurability in the face of complex timing and control requirements. This has led to a variety of systolic array architectures that accelerate extremely specific computational tasks. However, solving these configurability issues could open the door to a diverse set of new capabilities on mobile platforms.Edward A Lee.
Three-Chip System Synthesizes Human Speech.Electronics, Pages 109-116. 1978. John So.