Ned Bingham
2251 S Element Way Apt 204, Bloomington IN, 47403
(812) 606-2407
Highly accredited computer engineer with experience across the full stack including digital circuit design, computer architecture, assembly, systems programming, database systems, computer graphics, distributed systems, and both front and back end web development. Quick to learn, highly focused, and easily motivated. Open to criticism as an opportunity for self improvement. Ready to bring new ideas to the table and apply this extensive skill set.

Professional Experience

Broccoli []


Developed the key Intellectual Property for the first product, developed a course on self timed circuits to bootstrap the hiring pipeline, developed a thorough value proposition through in-depth market research, wrote a grant to the NSF Seed Fund, developed a full three statement financial model to project viability of the business, and continuous networking for customer relationship and customer product validation.

Bloomington, IN

Dec 2021 - Current

JRC Integrated Systems

Senior Microelectronic Design and Test Engineer (Contract)

Bloomington, IN

Feb 2024 - Current


Principal Backend Engineer

Mentored and managed six team members. Three were promoted to leadership roles and are now managing small teams while owning and developing major subsystems of the product. Designed, and implemented a system for routing user requests in a large scale Content Distribution Network (CDN), a major feature required for final product functionality. Deployed the staging and production clusters with a cross-functional team finalizing the product allowing the rest of the engineering org to push updates to production through CI/CD processes.


Feb 2022 - Jun 2023


Master of Business Administration, Entrepreneurship, Marketing

Indiana University, Kelley School of Business (transcript)

Corporate Finance Academy, Kelley Merit Fellow, Entrepreneurial Innovation Academy, Elevate Ventures Challenge First Place

Bloomington, IN

Aug 2022 - May 2024

PhD, Computer Engineering

Cornell University (visiting Yale University) (transcript)

Analyzed statistical behavior of program workload for optimizable features, invented a collection of arithmetic operators using those program workload features that doubled throughput per transistor and halved energy per operation on average compared to industry standard approaches.

New Haven, CT

Apr 2017 - Dec 2020

Masters of Science, Computer Engineering (GPA 4.00)
Bachelor of Engineering, Computer Engineering (GPA 3.29)

Cornell University (transcript)

Developed an automated formal synthesis engine for Quasi-Delay Insensitive circuits including a simulator, state space elaborator, and state conflict checker for Handshaking Expansions along with partial implementations for unique state encoding and guard strengthening.

New York, NY

May 2013 - Apr 2017

Ithaca, NY

Aug 2009 - May 2013

Selected Publications

Self-Timed Length Adaptive Arithmetic []

Cornell University Dissertations Publishing
Edward Arthur Bingham


A Systematic Approach for Arbitration Expressions [doi, html, pdfdoi:10.1109/TCSI.2020.3011552]

IEEE Transactions on Circuits and Systems I
Ned Bingham, Rajit Manohar


Self-Timed Adaptive Digit-Serial Addition [doi, html, pdfdoi:10.1109/TVLSI.2019.2918441]

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ned Bingham, Rajit Manohar


QDI Constant Time Counters [doi, html, pdfdoi:10.1109/TVLSI.2018.2867289]

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ned Bingham, Rajit Manohar



Introduction to Self-Timed Circuits [course]

Broccoli, LLC
Ned Bingham

Bloomington, IN

May 2023 - Aug 2023

CS 5620: Computer Graphics [course webpage,,]

Cornell University
Craig Gotsman, Ned Bingham

New York, NY

Aug 2015 - Dec 2015

Selected Projects

Floret (Automated Cell Layout, EDA Tool Design)

A gridless cell layout engine using a constraint-graph channel router derived from the Glitter paper.

Bloomington, IN


Stanford's Braindrop Project (Memory Systems, Cell Layout, Tapeout)

Collaborated on the tapeout of the Braindrop chip, and was responsible for the design, verification, and layout of the asynchronous memory.

New York, NY

2015 - 2016

Haystack (QDI Circuits, Compilers, C++)

A synthesis engine for Quasi-Delay Insensitive circuits. Circuits are described as an abstract behavioral model in Communicating Hardware Processes (CHP) and formal transformations are applied to synthesize a digital circuit.

New York, NY

2013 - 2015

Blaze Game Engine (C++, GLSL, OpenGL)

A rendering engine for large randomly generated planets with smooth level-of-detail transition from space to ground.

Bloomington, IN

2006 - 2015

Standard Core (C++)

A full container library implemented as an educational exercise, implementing generic slices using any container of iterators.

2006 - 2020 (PHP, CSS, Javascript, Web Design)

A recipe website that calculates the ingredients that are more likely to be in a recipe with the ingredients already selected.

New York, NY


Toy Neuron (Small Electronics, C)

Four small neuron toys that can be connected together to form a simple neural network. Upon firing, a set of LEDs along the axon and dendrites light up in sequence to show a depolarization travel from one neuron to the next.

Ithaca, NY

Jan 2012 - May 2012

Other Skills

VLSI, Digital Logic, Verilog, Spice, Place & Route, Floor Planning, Java, Python, Perl, Matlab, SQL, Specman E (verification), Git, Slurm, Cadence Virtuoso, Magic VLSI, Blender, 3DS Max, Maya, Compilers, Distributed Systems, Flink, Terraform, Ansible, MongoDB, Redis, AWS, Gitlab CI, Kafka, GRPC, Go, Grafana, Datadog, Protobufs, Docker, Kubernetes