Corporate Finance Academy, Kelley School of Business Merit Fellowship Award
Analyzed statistical behavior of program workload for optimizable features, invented a collection of arithmetic operators using those program workload features that doubled throughput per transistor and halved energy per operation on average compared to industry standard approaches.
Developed an automated formal synthesis engine for Quasi-Delay Insensitive circuits including a simulator, state space elaborator, and state conflict checker for Handshaking Expansions along with partial implementations for unique state encoding and guard strengthening.
